1. Field of the Invention
The present invention relates to a differential amplifier.
2. Description of the Related Art
A differential amplifier outputs an output signal corresponding to a potential difference between two input signals and is widely used in integrated circuits.
A differential amplifier 100 installed in LSI (Large Scale Integrated circuit) is typically composed of a pair of PMOS transistors 101 and 102 whose sources are coupled to a common node and a PMOS transistor 103 inserted between the common node and a power supply terminal 104 having a power supply voltage VDD, as shown in FIG. 1. Input voltages VIN+ and VIN− are supplied to gates of the PMOS transistors 101 and 102, respectively. A constant bias voltage is applied to the gate of the PMOS transistor 103. The PMOS transistor 103 functions as a constant current source to send a constant bias current IBIAS to the sources of the PMOS transistors 101 and 102.
If the input voltage VIN+ is lower than the input voltage VIN−, the whole of the bias current IBIAS flows through the PMOS transistor 101, and is taken out as an output current IOUT+. On the other hand, if the input voltage VIN+ is higher than the input voltage VIN−, the whole of the bias current IBIAS flows through the PMOS transistor 102, and is taken out as an output current IOUT−. When the output currents IOUT+ and IOUT− flow into loads, an output of the differential amplifier 100 can be taken out also as a voltage. It should be noted that the differential amplifier can be formed of not PMOS transistors but NMOS transistors.
In order to normally operate such a differential amplifier, the two input voltages supplied to the differential amplifier need to be limited to a certain range. That is, it is not allowable that the two input voltages extend to the entire range between a ground voltage VSS and the power supply voltage VDD. For example, the two input voltages VIN+ and VIN− of the differential amplifier 100 shown in FIG. 1 need to be higher than the ground voltage VSS and lower than the voltage VDD−(VGS+VDS(SAT)). Here, the VDS(SAT) is the voltage between the drain and source of the PMOS transistor 103 when the PMOS transistor 103 is used in a saturation region. The VGS is the voltage between the gate and source of the PMOS transistor 101 (or the PMOS transistor 102) when the bias current IBIAS flows through the PMOS transistor 101 (or the PMOS transistor 102). Similarly, when the differential amplifier is formed of NMOS transistors, the input voltages VIN+ and VIN− need to be higher than the VSS+(VGS+VDS(SAT)) and lower than the power supply voltage VDD. The limit on the input voltage of the differential amplifier reduces the free degree of the design of the differential amplifier, and is not desired.
A CMOS operation amplifier circuit is described in Japanese Laid open Patent application (JP-A-Heisei 3-62712). In this conventional example, an allowable range for the input voltage of the differential amplifier is extended. The differential amplifier is composed of a pair of P-channel transistors for receiving input signals, a pair of N-channel transistors for receiving the input signals, and a circuit for synthesizing the outputs of the transistor pairs. The P-channel transistor pair and the N-channel transistor pair are different in the allowable range for the input voltage. Thus, the differential amplifier can be operated if the two input voltages are within the voltage range in which at least one of the P-channel transistor pair and the N-channel transistor pair can be operated.
In the differential amplifier, it is also desired that the power consumption is small in addition to the wide allowable range for the two input voltages. Since a large number of differential amplifiers are used in the LSI, it is extremely effective for the reduction in the power consumption of the LSI that the power consumption is small.